The present invention relates to a multilayer capacitor, in which a plurality of dielectric substrates having internal electrodes on the main surfaces thereof are laminated and capacitance is generated between the facing internal electrodes, and a mold capacitor having the multilayer capacitor built-in.
In an electronic device such as power supply, modem or the like, it is common to use a capacitor with a plurality of electronic parts in order to remove noise or to cut direct current. Following the rapid globalization in recent years, the size and cost reduction of an electronic device is highly demanded, and, accordingly, the size and cost reduction of electronic parts is also highly demanded. In addition, since the automatic mounting reduces cost and mounting area, surface-mount electronic parts are also highly demanded. Furthermore, incompatible features such as high performance, the reduction of feature fluctuation, the improvement of durability or the like are also highly demanded. Particularly, since a capacitor is widely used for the power supply or noise removal of plasma display, large-scaled liquid crystal display or the like, the high capacitance and high withstand voltage of the capacitor is also demanded.
FIG. 13(a) is a side cross-sectional view of a multilayer capacitor in the related art. FIG. 13(b) is a cross sectional view of the multilayer capacitor taken along the line G—G in FIG. 13(a). The multilayer capacitor 100 includes a multilayer body 110 formed of a plurality of laminated dielectric substrates 101. A plurality of divided internal electrode 102 is formed on the main surface of each dielectric substrate 101 forming the multilayer body 110. The multilayer body 110 is formed substantially in a cuboid, and a pair of external electrodes 103 is provided at both side surfaces, which face each other in the longitudinal direction of the multilayer body 110.
The multilayer capacitor 100 is formed by laminating a plurality of dielectric substrates 101, and the internal electrodes 102 are formed on the dielectric substrates 101 by screen printing, decalcomania, paste application or the like. That is, the dielectric substrates 101 having the internal electrodes 102 on the surface thereof are laminated so as to form the multilayer body 110.
In the multilayer capacitor 100 constructed as above, capacitance is generated between the layers of internal electrode 102 formed on the different dielectric substrates 101, and the summed capacitance contributes to the high capacitance of the capacitor (for example, see JP-A-2001-284157).
In addition, if voltage is applied to the multilayer capacitor 100 constructed as above, stress caused by piezoelectric effect is generated at certain portions. The stress is biggest in the vicinity of the central portion of the multilayer capacitor 100. Therefore, the stress influences most in the vicinity of the central portion of the multilayer body 110. In order to improve the withstand voltage of the multilayer capacitor 100, it is required to improve the withstand voltage of the multilayer capacitor in the vicinity of the central portion. Furthermore, what make the capacitor weak to the stress in the improvement of withstand voltage is, firstly, the voltage applied to the portions between the adjacent internal electrodes 102 formed on the main surface of the same dielectric substrate 101, and, secondly, the voltage applied to the portions between the adjacent internal electrodes 102 formed on the dielectric substrates 101 overlapped in the laminating direction.
However, in the multilayer capacitor in the related art, the internal electrodes 102 are formed on the main surface of each dielectric substrate 101 at regular intervals with inter-electrode distance W therebetween. Therefore, the inter-electrode distance W between the adjacent internal electrodes 102 formed on the same dielectric substrate 101 is equal throughout the multilayer capacitor 100. In addition, since each laminated dielectric substrate 101 has the same thickness, the interval between the internal electrodes 102, which are formed on the different dielectric substrates 101 and adjacent in the laminating direction, is also equal in the laminating direction.
Due to the above fact, when a certain voltage is applied to the multilayer capacitor 100, there occurs a difference between the withstand voltage in the vicinity of the central portion of the multilayer capacitor 100, which is the weakest portion to stress, and the withstand voltage in the other portions. In addition, the withstand voltage in the vicinity of the central portion, which is the weakest portion to stress, becomes the withstand voltage of the multilayer capacitor 100. As a result, there is a case that cracks are caused in the internal electrode due to the stress caused by the piezoelectric effect. Furthermore, there has been a problem in that countermeasures for achieving the high withstand voltage and high reliability have never been devised sufficiently.
In order to solve the above problem, it is possible to improve the withstand voltage by increasing the area of the main surface and the thickness of the main surface of the dielectric substrate 101. However, in this case, the size of the multilayer capacitor 100 increases, which is incompatible with the recent trend requiring the size reduction of a device. As a result, it is demanded to develop a multilayer capacitor capable of improving the withstand voltage and achieving the high capacitance with no size increase.